Speed Comparison Of 32×32 Multiplier using Vedic Mathematic Techniques
Hema S.1, Geethapriya S.2, Vijayalakshmi G.3
1Hema S., ECE Department, Veltech college, Chennai, India.
2Geethapriya S., ECE Department, Veltech college, Chennai, India.
3Vijayalakshmi G., ECE department, Veltech college, Chennai, India.
Manuscript received on November 11, 2013. | Revised Manuscript received on November 15, 2013. | Manuscript published on November 25, 2013. | PP: 57-60 | Volume-2 Issue-1, November 2013. | Retrieval Number: A0578112113/2013©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers . So the Implementation of Vedic Mathematic techniques and their application to the complex multiplier provide substantial reduction in propagation delay ,execution time in comparison with the existing methods. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. The techniques described in this paper are Nikhilam Sutra, Urdhva Tiryakbhyam and Karatsuba-ofman and the performance analysis of these techniques is obtained. Modelsim tool is used for simulation and the results obtained are compared on the basis of time delay of multiplication.
Keywords: Vedic mathematics, urdhva triyakbhyam sutra, karatsuba – ofman algorithm