Design Low Power Full-Adders for Arithmetic Applications
Hajar Zare Bahramabadi1, Hamidreza Dalili Oskouei2, Asghar Ebrahimi3
1Hajar Zare Bahramabadi, Electronic engineering Department, Islamic Azad University Bushehr Branch, Bushehr, Bushehr, Iran
2Hamidreza Dalili Oskouei, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran
3Asghar Ebrahimi, Electronic engineering Department, Bushehr Branch Islamic Azad University, Bushehr, Iran
Manuscript received on October 11, 2013. | Revised Manuscript received on October 15, 2013. | Manuscript published on October 25, 2013. | PP:78-81 | Volume-1, Issue-12, October 2013. | Retrieval Number: L05221011213/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and COUT.
Keywords: A CMOS full adder, XNOR-XOR gate, low power full adder